I am using ADSP-21363 processor. I want to configure SPI as master to trasmit data to a slave device using DMA and disable the SPI port after the transfer is over. Can I disable the SPI port in the DMA completion interrupt service routine ?
In all SHARC processors except ADSP-2146x, the SPI DMA interrupt occurs when the DMA count reaches zero. DMA count becomes zero as soon as the last word is transferred from the memory to the DMA FIFO. Only relying on the DMA completion interrupt does not ensure that the last bit of the last word is shifted out on the external interface. Thus, before disabling the SPI port in the interrupt service routine, one should poll the SPIFE (bit 7) of SPISTAT register and wait till it's set. This bit is set when the transfer is complete on the external interface.
In ADSP-2146x processors, there is bit called INT_ETC(bit 3) in the SPIDMAC register that decides whether the DMA interrupt will occur either when the transfer on the external interface is complete (INT_ETC=1) or when the DMA count reaches zero similar to other SHARC processors ( INT_ETC=0) . The SPI port can be directly disabled inside the ISR with INT_ETC bit set. This helps to save the core's time that would have wasted in polling the status bit.
Then what is the different between SPIF bit and SPIFE bit ?
SPIF bit makes sure that one word has been sent out of the Rx/Tx register. While SPIFE bit makes sure that all the word unrtil the last but has been shifted out of the shift register and out of the external interface completely.
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