Recently I have a project and wana to use BF561 as its central processor. When learning BF561, I was confused with following quesetions:
(1) Is there voltage regulator in 600MHz speed grade. In the Hardware reference, I see there is VR_CTL register to control the regulator, and the FREQ bits is 11 by default, which means the VDDINT is not bypassed. But in BF561 datasheet, there are saying that when the processor working in 600MHz, the regulator is not used. Can you explain why?
(2) How the two core do operating mode transitons. In the hardware reference, there are saying "each core runs at the same core clock frequency and in the same power mode". From the mannal, I learn that one core can set the related register bits and do special code squence, and then the transiton can happen. But how do the other do mode transition, and how the two cores work when they do mode transition.