We have successfully developed an ADC board with AD9517-3 onboard. Our goal is to make two such boards work coherently. As far as I understand, ~SYNC signal cannot be used for this purpose. The datasheet says the following.
There is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9517.
Even if we make system controller chip release ~SYNC signals on both boards at the same instant, they won't always be in phase, will they? As far as I understand, both boards will be either in phase, or one board will be ahead of the other by 1 VCO clock cycle, and this will change randomly every time we turn the system on.
So, what measures can we take to make two coherent PLLs?
Thanks in advance!