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ADSP 21469 SPI Slave Boot

Question asked by Hfuhrhurr on Apr 20, 2012
Latest reply on Jun 4, 2012 by Mitesh

Hi all,

 

I have a problem with booting the ADSP 21469 from an ARM Cortex M3 processor (Stellaris LM3S).

The DSP is clocked by a 12.288 MHz Oscillator and CLK_CFG1-0 is 1 0, so the DSP is running at 16x12.288MHz

 

Here's what I am doing

 

  • Reset the DSP
  • wait for RESETOUT being deasserted
  • for safety, wait another microsecond
  • transfer data to the DSP via the SSI (SPI) interface

SSI Settings:

SSI_FRF_MOTO_MODE_3 (CPHASE and CPOL = 1)

16 bit wordlength

SPI rate 50kHz (500kHz and 5MHz also tested)

  • transferred data

0x66AA, 0x22CC, 0x4488

0xBB33, 0xDD55, 0x11EE

which is bitreversed

0x5566, 0x3344, 0x1122

0xBBCC, 0x99AA, 0x7788

 

Only these 6x16-bit words are transferred.

According to the 16-bit packing rules, this should result in

0x112233445566

0x778899AABBCC

 

When I look into the P-MEM of the DSP at 0x8c000 after this procedure, I see



Dumping range 0x0008c000 - 0x0008c00b by 1 (Hexadecimal)...

    0x556655660000

    0x112233443344

    0xBBCCBBCC1122

    0x778899AA99AA

    0x556655667788

    0x112233443344

    0xBBCCBBCC1122

    0x778899AA99AA

    0x000000000000

    0x000000000000

    0x000000000000

    0x000000000000

 

It looks like the values itself are transferred correctly, however they are scrambled and duplicated in the buffer.

The SPI signals look like this

DSPBootSPITiming.png

What you see in the screenshot are the first two 16-bit words 0x5566 and 0x3344.

I modified the pause between two 16-bit transfers from almost no pause at all to long pauses as seen in the image, makes no difference.

 

Does anyone have an idea what's wrong?

 

EDIT: I had a closer look at the timing between the SPI DS and SPICLK

DSPBootTiming_DS_CLK.png

The two signals at the top are SPIDS (yellow) and SPICLK. There's exactly one half SPICLK cycle between asserting SPIDS and the first CLK edge. Would that be sufficient?

 

Best regards,

 

Rainer

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