is it possible to connect BF537 processor to PEX8311 via local bus interface of PEX8311?
is there any such an example?
I am not familiar with the PEX8311 PCI Express to Generic Local Bus Bridge and if its possible to connect it to our BF537 processor. I would recommend contacting the company that produce the PEX8311 bridge (PLX Technology) with this question.
Looks like they have mentioned membership requirements for "PEX 8311 Technical Documentation". Without interface details, we cannot really comment, as Colin said. Also, you could not simply post their proprietary information here, so you need to talk to your vendor in any case.
External Controllers for LAN and USB can be interfaced via Async Bank of Blackfin, and there are daughter cards available for that (you use this port typically to interface with Flash or SRAM). If interface is not glueless, you might need an FPGA in between.
I already contacted with them and requested support. But they are also indicates they are not familiar with Blackfin. They just indicated it can be connected to the Blackfin. Below is the comment they provided:
I'm afraid that we know very little about the operation of the BF537 EBIU but the 8311 local bus is extremely flexible so it is highly likely that you will be able to interface the processor to the 8311. Looking at the description of the signalling it looks relatively straight forward but may need to register some of the control signals to ensure they meet the 8311 requirements.
You don't state whether you need the 8311 to act as an endpoint or a root complex. The 8311 can do either mode. For endpoint mode PLX provides drivers for Windows and Linux as part of the SDK. As the EBIU bus is only 16 bits wide you will need to change the default setting for the local address space on the 8311 to 16 bits - this can easily be done in the EEPROM.
I think it is unlilely you require this but in the case of root complex mode you will have to write code on your Blackfin to enumerate any PCIe devices which are downstream of the 8311. In addition, the 8311 bus mastering interface assumes that the bus mastering CPU is 32 bits wide so you will have to add some additional logic to combine two 16 bit data accesses into a 32 bit one.
I can provide PEX8311 datasheet to you if you like after getting permission from PLX. I feel asncronous memory interface should be connected to the this chip. I have litte time to finalize design. If i can directly interface with PEX8311 i will remove FPGA and additional memory blocks and directly send data to pc.
I assume they know our interface (so it sounds promising) because we have used their different controllers I stated above via EBIU, but we still cannot state from our end. What you could do is to ask them if you could send it to Private Support at ADI (so you do not need to post their datasheet here). If they agree, you could open a ticket at email@example.com and someone will review and comment about the interface.
I sent an e-mail to processor.support. Furthermore, i would like to learn which plx chips you used with EBUI before. I just need PCIe interface with blackfin. If one of them is already used for the same purpose i can use it as well.
No return from both Engineer zone and processor.support.
Are these explanations correct for BF609 as well? We need to interface with pcie bus by this DSP again.
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