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spidev performance: time between cs active and sclk activity

Question asked by StefanW on Apr 20, 2012
Latest reply on Apr 23, 2012 by ScottJiang



I have a question related to the performance (speed) of spidev. On an oscilloscope I can see that there is a >15us delay between each chip select becoming active and the first cylce of the serial clock. After chip select get deactivated there another >20us delay before the next chip select becomes active.

Can these delays be configured somewhere or can they be reduced?

I transmit only 2 bytes with each transfer, so the transfer speed is regulated by those delays far more than by the speed_hz setting.

I'm using uClinux 2009R1 on a bf537 custom board, two spidev devices are active.


Best regards,