We only have two devices hooked up to SPI bus. Among them, ADuC7124 is slave and one CPLD is master. The ADu7124’s SPI bus
mode is chosen as slave, phase mode:0, polarity: 0. Each data transfer between them is 16 bits. We have to pull CSn high at the rising edge of the last clock since there is no falling edge at the last clock. If we pull CSn high at the rising edge of the last clock, the timing, tSFS would be violated. Do you think that CSn can constantly be pulled low? If so, we don't need to worry about the timing issue of CSn. We just try to do something like this and found that ADuC7124 can not properly receive the data. Please help me out. Your support is highly appreciated. Thanks!