I am using the AD9548 to build a GPS locked reference clock with extended holdover capability.
I found AN-1002 describes a possible solution by using a lower grade OCXO and an adaptive correction algorithm to compensate for any drift if GPS signal is lost.
If I understand the application note right, I need to put the PLL in free-run mode and close the loop externally via the serial port using a processor. This way I can seamlessly control the DDS either with the tuning word from the phase comparator (if GPS is valid) or with values from the adaptive oscillator model (in holdover).
Here is the section from AN-1002 which I would like to clarify:
"Initialization occurs the moment the GPS receiver first indicates lock. The external processor starts monitoring elapsed time and the AD9548 digital PLL automatically starts to acquire the 1 pps GPS signal. By programming the AD9548 holdover accumulation timer so that it provides updates at intervals of 1 sec, the processor can read the currently active frequency tuning word from the AD9548 (System Parameter Y) on a second-by-second basis. The processor maintains a running 100 pt MA of the Y values and writes each new MA value to the AD9548’s free-run frequency tuning word register."
- What is the required operating mode of the AD9548? Is it free-run?
- How can I read the current frequency tuning word from the AD9548? (It appears the tuning word doesn't update in free-run mode)
- How do I set the DDS frequency?
- How do I program the update intervals of 1sec?
I am using the evaluation board to check/test the functionality.