We work with our own custom board with four TigerSHARC processors (ADSP-TS201S) on it arranged in multiprocessor cluster configuration. We have about twenty boards and on the half of them there is a problem: sometimes one of the processors don't boot correctly. I explored it a little bit and found the following issues that troubled me. There is some pattern but I don't quite understand it. I mean on three boards we have problem with the same one processor but on the other three we have problem with another one. Also on some boards processor don't boot 1 of 20 or even 40 times on the others 1 of 2 or 3 times. There are boards on which I can connect to troubled processor with emulator when it doesn't boot successfully, holt it and watch some info but on the other boards I cannot connect to troubled processor at all and when I try to do so the whole JTAG chain gets dead with messages like "Device x: Emulator HW could not scan EMUSTAT register" and "JTAG scan failed...". In that case I can only use a "Do not disturb" type of connection to work with other three processors. So when I connect to troubled processor with emulator when it doesn't boot successfully and look at the internal memory I see part of the boot kernel and many "????" sign where the kernel code should be. I also see something like this on boards where I cannot connect directly to troubled processor so I connect to other one and watch through multiprocessor memory space aka through cluster bus. And one more thing: when I try to request software reset writing 1 to SWRST bit in EMUCTL register, 15 seconds or so nothing really happens, then some registers change their values and some initialization of peripherals takes place, so then I request software reset again and voila everything works correctly. I tried that trick about 50 times on 2 or 3 different borads and every time it worked exactly the same I mean fine: processor booted successfully and application was working as expected. So I thought that I could rule out possible problems with power sequence, reset condition or PLL problem. By the way I cannot use TM3 mode to observe directly what's going on with clocks but indirect observations suggest that everything seems to be okey at least as far as I understand but maybe I am wrong, am I? So can you suggest what may be wrong with our boards or what else I can do to explore the problem for better understading or maybe you even know some magic fix for that problem?! By the way I have some screenshots and logs from internal memory of the troubled processor so if it somehow can help I can send them to you. Oh, I forgot to mention one thing, I experimented with different SCLK ratio values I set minimum possible value of 4 (we work from 83.3 MHz oscillator) but the picture didn't really change...