Hello,

The System clock period is between 500 Mhz to 1GHz.

But, What better frequency for a frequency reference of 1 PPS and external Clock of 10MHZ (Xtal Input)

thankful,

Bruno Braga

Hello,

The System clock period is between 500 Mhz to 1GHz.

But, What better frequency for a frequency reference of 1 PPS and external Clock of 10MHZ (Xtal Input)

thankful,

Bruno Braga

Hi Bruno,

To attain the greatest amount of frequency accuracy, you will use the lower system clock frequency because your frequency resolution is f_sys/2^(48) Hz for the AD9548. However, the frequency offset you will actually see on the output is based on the amount of rounding that is done to attain your used frequency tuning word. For example with a system clock of 1GHz and an output frequency of 10 MHz the calculated FTW is 2814749767106.5601 which gets rounded to 2814749767107 and produces and output frequency of 1e9 * 2814749767106/2^(48) = 10000000.000001563 Hz which is 1.5627592802047731e-07 ppm of frequency offset. While with a system clock frequency of 500 MHz and an output frequency of 10 MHz the calculated FTW is 5629499534213.1201 which is rounded to 5629499534213 and produces an actual output frequency of 500e6 * 5629499534213/2^(48) = 9999999.9999997877 Hz which is -2.1234154701232911e-08 ppm of frequency offset. With your output frequencies, using 2^(n) frequency system clock will yield perfect results for output frequency accuracy (i.e. use a system clock of 2^(29) and you will get 0 ppm offset on both the 1 pps and 10 MHz output). Unfortunately, this is not practical.

If you are using the AD9548 in active mode, then the DPLL will modulate the FTW to lock to your reference and the average frequency of your output will be synchronized with the average frequency of your input and in this case you will benefit from the better frequency resolution. So I recommend a 500 MHz system clock frequency.

Hi, neilw.

Thank very much by response.

Still there are doubts for calculate o value of Phase Lock Threshold, Phase Lock Fill Rate and Phase Lock Drain Rate. And more Frequency Lock Threshold, Frequency Lock Fill Rate and Frequency Lock Drain Rate.

Which values can for signal of output is good?

Because I'am trainne and there is many doubts.

Thankful,

Bruno Braga

Hi Bruno,

With a 1pps reference you will want to use a lower loop bandwidth in this application. However, this means that you will have to have a stable system clock input (your 10 MHz external clock). Please see this App Note that elaborates on system clock stability requirements for low loop bandwidth applications

Hi Bruno,

The lock detect values will be programmed based on the expected amount of jitter on your reference input. This App Note explains the the phase and frequency detectors of the AD9548 and their reaction to different types of random jitter.

Hi Bruno,

To attain the greatest amount of frequency accuracy, you will use the lower system clock frequency because your frequency resolution is f_sys/2^(48) Hz for the AD9548. However, the frequency offset you will actually see on the output is based on the amount of rounding that is done to attain your used frequency tuning word. For example with a system clock of 1GHz and an output frequency of 10 MHz the calculated FTW is 2814749767106.5601 which gets rounded to 2814749767107 and produces and output frequency of 1e9 * 2814749767106/2^(48) = 10000000.000001563 Hz which is 1.5627592802047731e-07 ppm of frequency offset. While with a system clock frequency of 500 MHz and an output frequency of 10 MHz the calculated FTW is 5629499534213.1201 which is rounded to 5629499534213 and produces an actual output frequency of 500e6 * 5629499534213/2^(48) = 9999999.9999997877 Hz which is -2.1234154701232911e-08 ppm of frequency offset. With your output frequencies, using 2^(n) frequency system clock will yield perfect results for output frequency accuracy (i.e. use a system clock of 2^(29) and you will get 0 ppm offset on both the 1 pps and 10 MHz output). Unfortunately, this is not practical.

If you are using the AD9548 in active mode, then the DPLL will modulate the FTW to lock to your reference and the average frequency of your output will be synchronized with the average frequency of your input and in this case you will benefit from the better frequency resolution. So I recommend a 500 MHz system clock frequency.