We are planning to use the ADA4817 1GHz Fast fet op-amp (amazing device that it is!). We would like to use it as a 2:1 multiplexor.
We note that it can be powered down (with Iq = 1mA), however there is no information on the output topology when powered down.
Assuming that we will have a series resistor between each output and a common summing point (which happens to be a ADA4939 differential amplifier), do you have any idea about the following points:
1. What is the load presented by the powered-down op-amp output (as in R//C) ?
2. If the output is a relatively low impedance (ie 100 - 1k), how variable is it from device to device and over temperature
2. What is the effective output noise (nV/rtHz would be good) for a powered down op-amp?
Thanks for any help.