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ADAU1966 Audio DAC documentation for I2C seems all messed up

Question asked by SteveDC on Apr 1, 2012
Latest reply on Feb 4, 2013 by ColemanR

I am looking through the datasheet for the ADAU1966 audio DAC trying to get I2C working but there seems to be a lot of errors in the datasheet.


For example, on page 17 it references Rb/W being low for the first address frame but the nomenclature in the diagram on page 18 shows R/Wb. I assume R/Wb is really the intent (as per the I2C specification).


Next, on page 18 figure 13 for a read shows the AD0/AD1 bits being in the MSB positions for the first chip address cycle (frame 1) but in the LSB positions for the second address cycle (frame 3). I don't think this is correct.


I am still trying to get my code working correctly since my current implementation does not do repeated starts, so I am adding this, but I wanted to get some feedback on what the correct address control bit positions are for read operations?