I'm developing a VDK-based project for the BF534 which must reside in and run from SDRAM. One small section (a fast ISR) resides in L1 memory and is initialised at run time from SDRAM. I have achieved this by editing the LDF file so that sections such as L1_code are mapped to SDRAM0 instead, e.g.
} > MEM_SDRAM0
I know this is rather a kludge but as long as I am careful not to remap cache or stack sections which are mapped to L1 memory this works. I have instruction and data caches enabled and it all works fine. I have hit a problem when I enable the Generate a customizable CPLB table option. This causes the CPU to generate a core fault and start running the program out of control when I load the program via the emulator, even with the default CPLB table file, which may be down to my unconventional re-mapping of memory. In any case, the remapping is tedious as I have to redo it every time something causes the LDF file to be re-generated.
Is there a better way of forcing the IDE to put program code and data (including libraries, startup code and non-editable VDK code) where I want it in SDRAM and not in default L1 memory?
Adding the USE_SDRAM pre-processor macro to the LDF pre-processor macro definitions doesn't appear to do anything. I have set the program to start in external memory at address 0x40 and the linker puts some startup code in the SDRAM and everything else in L1 memory. The documentation doesn't seem very clear on this.
Are there any examples available?