In BF60x there is no CDPRIO bit in SMC registers to control the priority of DMA and Core accesses to SMC. However the cross-bar/arbiter in the BF60x follows a round robin algorithm to give AXI masters (Core0, Core1, DMA, etc.) access to slaves like SMC. By default each master has number of slots out of total 32 slots assigned to it for accessing SMC slave as shown in the table below. In this default configuration all the masters can access the SMC in round robin fashion so if all the masters have equal number of slots all of them will get equal chance to access the SMC slave. But if user wants to elevate the priority of any particular master like Core0 then more number of slots should be assigned to Core0. In fact all the slots can be assigned to a single master so in that case other masters cannot access the SMC at all but that is not recommended as it can cause a system hang if master with zero slots is one of the Cores. This is because if master does not have a slot and it tries to access the slave then the master will keep on waiting for the response from the fabric (crossbar/arbiter) for the issued read/write access. So in case of Core if no slot is provided and Core access to SMC is done the Core will hang and pipeline won’t move.
The slot distribution described in the table is default, and that can be changed through MMR programming. By this way we can elevate the priority of any master.
The priority for read and write accesses to the slave are programmable separately. In order to change slots given to different masters, user has to write to SCB arbitration register multiple times to program different slots as the address map does not have sufficient space for each value to be addressable separately, some addressing information is encoded in the write data when updating values.
For example to change the slots assigned to different master for read accesses to SMC user has write to SCB0_ARBR1 register multiple times with each write specifying the mater ID number and slot number.
The piece of code below assigns all the slots to Core. Note that master ID for Core0 is 0 and slot number is passed through variable ‘i’
#define CoreMasterID 0 //SI0: Core0 master ID
unsigned int temp;
for(int i =0 ; i<= 31; i++)
temp = (CoreMasterID & BITM_SCB_ARBR_SLAVE) | ((i<<BITP_SCB_ARBR_SLOT) & BITM_SCB_ARBR_SLOT);
*pREG_SCB0_ARBR1 = temp;
Register for programming the slots for write accesses is SCB0_ARBW1.