Can you please confirm the proposed placement of bypass capacitors for ADSP-21362/3 for LE_QFP package?
For a BGA, the best method would be to place caps at each power pin. This is not always possible. The second method is to place caps along each of the 4 edges of the device. For the QFP, some but not all can be on the back side underneath the chip. You might want to aim for at least 2 on each side for each of the two voltages. That would be 16 caps but if they do not have space, about 8 or 10 caps might work.
DeepV's advice is good, but there are a few more things to consider.
The first rule of decoupling is that it's mostly about lead inductance. The value of the capacitor is less important.
This means that you want to connect each capacitor with very short leads directly to a plane. I often just slightly overlap a via to the pad of the capacitor. In many cases, I use two vias, one on each side of the capacitor pad.
Smaller packages have less inductance. 0603's work well on the bottom side of 1mm pitch BGAs, 0402 work much better for 0.8mm pitch BGAs, 0603s usually work well for QFPs. I usually mix 10nF & 100nF values with a few bulk 4.7uF ceramics.
I decouple BGAs on the bottom side of the pcb, The power and ground connections are usually located in the middle of most devices so this is usually the best location. It also makes signal routing easier. QFPs are actually harder to route. In this case, I follow DeepV's suggestion of placing caps on the top layer fairly symetrically on all 4 sides. It's important to fanout the DSP power and ground pins quickly. I often make a serpentine power plane to deal with Vio and Vcore. I think its harder to decouple a QFP, but it may be less critical since they are almost always slower devices. In some cases, you may only need a four layer pcb (if you serpentine the power plane), but you NEED planes for all Vio, Vcore and GND.
BGAs have a big advantage with lead inductance which is why the go-fast parts are not sold in QFP.
The last thing item to watch for is the clearance setting for the vias. CAD systems often have the clearance see too large around vias. This makes your internal planes look like they were "shotgunned". You want your vias direct connected (not relief-connected) and you want the via clearance to be the same as your minimum trace spacing (.1 to .2mm, 4 to 8mil). REMEMBER, ITS ALL ABOUT INDUCTANCE!
A good reference is High-Speed Digital Design - A Handbook of Black Magic by Johnson & Graham.
Danville Signal Processing
I would recommend that you try to keep the decoupling on the same side of the board, if at all possible. As Al has correctly pointed out, lead inductance is very important, however there is inductance in the small vias that might be buried in a pad of a BGA; internal switching frequencies will be present at the power pins, much higher frequencies than seen on the outside and you don't want to reflect these back into the power pin. If the power pins are in the outside ring of a BGA, I would try to fit the decoupling on the same side of the pcb. I would also try to reference the ground pin of the capacitor directly back to the closest ground pin of the device, creating the smallest and cleanest 'feedback' loop possible. If possible, you should avoid a loop through 2 vias back to the device.
The idea of mixing capacitor values is really good; this will reduce any chance of your best efforts actually causing ringing on the board!
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