Data Mirroring feature increases the flexibility of the pin muxing options with respect to the PPI Data pins. An MMR bit (DAT_MRR) is allocated for this feature, which if set, will mirror the bits D[15:0]. By default (DAT_MRR=0), the data bits behave as usual. DMIRR field enables mirroring (bit reversing) the data coming in or going out on the EPPI data pins, this feature is available in both transmit and receive case.
Using 16 data pins [15:0] of any PPI , MUX_SEL allows two 8bit cameras to be connected to one PPI, one of which can be operational at any given time. To select between the two camera options, a select line is also provided inside the PPI. The select line MUX_SEL is programmable and available in PPIx_CONTROL register. When MUX_SEL is enabled, there is no need to enable DAT_MRR separately and data mirroring is automatically enabled. For proper data connectivity, the pins of one camera should be connected to pins D[7:0] of EPPI in normal fashion(i.e. D0-D0, D1-D1,..D7-D7) with its frame sync and clock connected to FS1 and PPI_CLK of EPPI respectively. For other camera data pins have to be connected in bit reversed order to D[15:8] of EPPI meaning that D0 of camera is connected to D15 of EPPI, D1-D14, and so on. The frame sync and clock of second camera should be connected to FS2 and FS3 of EPPI which act as frame sync and clock for the EPPI respectively when MUX_SEL is set.
The following are the conditions in which the above scheme will be applicable
- All PPI signals are INPUT in this mode
- Only 8-bit data is supported
- Either frame-sync-less ITU mode or 1FS is used
- PPI needs to be disabled when the mux select is changed (frame needs to re-sync after re-enable). At least one frame will be lost in this process.
- Both the cameras have same frequency but are still asynchronous.