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Are there any pins associated with SMC multiplexed.

Question asked by Nabeel Employee on Mar 27, 2012

Yes, most of the pins of SMC are multiplexed with other peripherals on Port A and Port B. A3-A25 address lines, NORCK, AMSx, BG, BGH, ABE0 and ABE1 are available on port A and B, these pins must be set for SMC functionality using MUX and FER register before using the SMC.

 

The SMC design also internally multiplexes some signals on the same line. For example, the ARE pin for SRAM and the OE pin for NOR Flash device are muxed internally by the SMC before it drives it to the pads. The internal state machine ensures appropriate assertion and de‐assertion conforming to the device timing.


Table below shows the internal muxing scheme in SMC:

 

Async SRAM

Flash

Comment

A[25:1]

NOR_A[25:1]

Address

DQ[15:0]

NOR_DQ[15:0]

Data

AMS[3:0]#

NOR_CE[3:0]#

Chip enable

ABE[1:0]

       -

Byte enable

ARE#

NOR_OE#

ASRAM : Read enable

Flash : Output enable

AOE#

NOR_ADV#

ASRAM : Output enable

Flash : Address valid(Latch enable)

         -

NOR_CLK

Burst clock

ARDY#

NOR_WAIT#

Wait

AWE#

FLASH_WE#

Write enable

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