Yes, most of the pins of SMC are multiplexed with other peripherals on Port A and Port B. A3-A25 address lines, NORCK, AMSx, BG, BGH, ABE0 and ABE1 are available on port A and B, these pins must be set for SMC functionality using MUX and FER register before using the SMC.
The SMC design also internally multiplexes some signals on the same line. For example, the ARE pin for SRAM and the OE pin for NOR Flash device are muxed internally by the SMC before it drives it to the pads. The internal state machine ensures appropriate assertion and de‐assertion conforming to the device timing.
Table below shows the internal muxing scheme in SMC:
ASRAM : Read enable
Flash : Output enable
ASRAM : Output enable
Flash : Address valid(Latch enable)