AnsweredAssumed Answered

Configuring right justified ad1836 packets on EzKitbf561

Question asked by willrobot on Mar 27, 2012
Latest reply on Apr 12, 2012 by Prashant

Hi,

 

I'm trying to configure right justified packets on the ad1836 register. I do not had any luck though, I always get the packets left justified. As well is I2S right or left justified?

 

the configuration of the ad1836 is as in talkthrough: (whe I try right shift nothing change)

 

volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] =

{

                                        DAC_CONTROL_1   | 0x000, //was 0x020  

                                        DAC_CONTROL_2   | 0x000,

                                        DAC_VOLUME_0    | 0x3ff,

                                        DAC_VOLUME_1    | 0x3ff,

                                        DAC_VOLUME_2    | 0x3ff,

                                        DAC_VOLUME_3    | 0x3ff,

                                        DAC_VOLUME_4    | 0x3ff,

                                        DAC_VOLUME_5    | 0x3ff,

                    ADC_CONTROL_1   | 0x000, //was 0x000/1\

1B                                                                            

                                        ADC_CONTROL_2   | 0x180,//was 180/140 

                                        ADC_CONTROL_3   | 0x000

 

};

    // reset codec                                                   
    // set PF15 as output                                            
                   
   

 

    SSYNC();

    // clear bit to enable AD1836                                    


    bfin_write_FIO0_FLAG_S(bfin_read_FIO0_DIR() | 0x8000);

 

    SSYNC();

 

    // wait to recover from reset                                    

    for (wait_reset=0; wait_reset<0xf000; wait_reset++);

 

   // Enable PF4                                                    
                                          

    bfin_write_SPI_FLG(0x1010);

 

    // Set baud rate SCK = HCLK/(2*SPIBAUD)                          
     

    bfin_write_SPI_BAUD(0x0010);

 

    // configure spi port                                            
    // SPI DMA write, 16-bit data, MSB first, SPI Master             
        

    bfin_write_SPI_CTL(TIMOD_DMA_TX | SIZE | MSTR);

 


// Set up DMA2 channel 4 to SPI transmit                         
                        
    bfin_write_DMA2_4_PERIPHERAL_MAP(0x4000);

 

    // Configure DMA2 channel4                                       
    // 16-bit transfers                                              
                             
    bfin_write_DMA2_4_CONFIG(bfin_read_DMA2_4_CONFIG() | 0x0004) ;

 

    // Start address of data buffer                                  
               

    bfin_write_DMA2_4_START_ADDR((void *)sCodec1836TxRegs);

 

    // DMA inner loop count                                          

           

    bfin_write_DMA2_4_X_COUNT(CODEC_1836_REGS_LENGTH);

// Inner loop address increment                                  
   
    bfin_write_DMA2_4_X_MODIFY(2);

 

 


// enable DMAs                                                   
   

    bfin_write_DMA2_4_CONFIG(bfin_read_DMA2_4_CONFIG() | 0x0001) ;

    // enable spi                                                    
                         
    bfin_write_SPI_CTL(bfin_read_SPI_CTL() | 0x4000);

 

 

    SSYNC();

 

    // wait until dma transfers for spi are finished                 

    for (wait_dma_finish=0; wait_dma_finish<0xaff; wait_dma_finish++);

 

    // disable spi                                                   
                                            
    bfin_write_SPI_CTL(0x0000);

 

 

I think that is what it should be done.... obviously I'm missing something in the configuration

Outcomes