In BF60x EPPI, there is support for delayed start of the PPI Frame Syncs - PPIx_FS1 and PPIx_FS2.The PPIx_FS1D and PPIx_FS2D would be new programmable registers corresponding to PPIx_FS1 (HSYNC) and PPIx_FS2 (VSYNC). The first active edge of the internally generated frame sync is delayed by the amount programmed in these registers starting from the first PPICLK edge. The delay counter (which is the period counter itself, since they don’t run together) runs only for the first time and then shuts off till the PPI is re-enabled. The delay registers should be
programmed prior to the first PPICLK edge (similar to the width and period register).
In the scope captures attached, picture1 is the one without delay where the first FS is asserted after 15 PPICLK cycles(PPI needs 5 CLK cycles to start + FS period which is 10 in this case). In picture2, first FS arrives after 7 PPICLK cycles(5 initial CLKs + 2 CLKs programmed in PPIx_FS1D).