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BF60x EPPI new features

Question asked by vinodbableshwar on Mar 26, 2012

BF60x has three EPPI blocks. EPPI0 will support 24b wide data bus, while EPPI1 and EPPI2 will support 18b wide data bus. The EPPI modules have a PxP interface that is used to interface with the PxP crossbar and the Video Subsystem. The PxP interface is capable of running concurrently with the memory side bus – that is, same data can go over the PxP as well as on the DMA bus.


There are multiple enhancements in the EPPI functionality, like:

1. Improved granularity for EPPICLK (odd clock ratio between internal clock and internally generated EPPI clock)

2. Support for delayed start of Frame Sync - The first active edge of the internally generated frame sync is delayed by the amount programmed in   these registers starting from the first EPPI_CLK edge.

3. Extend Preamble support for HD formats - The EPPI supports preamble generation/detection and blank stripping for the two HD formats SMPTE 274M and 294M

4. Local pin muxing inside EPPI to enable data mirroring feature- The EPPI_CTL.DMIRR field enables mirroring (bit reversing) the data coming in or going out on the EPPI data pins.

         Pin Data     EPPI_DATA     EPPI_DATA

                           (DMIRR=0)      (DMIRR=1)

           15                 15                 0

           14                 14                 1

            .                    .                  .

            .                    .                  .

            0                   0                 15