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what are the modifications made and new features added to ADC Control Module (ACM) of BF60x processors?

Question asked by Prashant Employee on Mar 26, 2012

The ACM module on the BF60x processor is functionally same as ACM module on BF50x processor.

There have been only few changes and couple of enhancements over it's previous version.

 

A] Changes in the BF60x ACM module:

  • ACM_Timer's Trigger select Inputs: Out of total four Trigger Inputs, two of the them comes from processor PORT pin PG5 and PE8; while remaining two comes from Trigger Routing Unit (TRU) of the processor. The large number of Trigger masters virtually increases number of ACM Trigger Inputs.

  • Improved ACM Clock Granularity:

In BF50x processor, ACM clock is calculated as: ACLK = SCLK / (2 × (CKDIV+ 1).

So, System clock (SCLK) is always divided by an even divider to generate ACM clock.

But in BF60x, the ACM clock is calculated as ACLK = SCLK1 / (CKDIV + 1) allowing odd dividers as well, thereby increasing the ACM clock granularity.

 

 

B] Enhancements in the BF60x ACM Module:

  • Gated clock mode support: The ACM Clock can be gated during inactive CS interval. The ACM Control register provides a bit, CLKMOD, to use this feature

  • Inclusion of Event Order Registers: Sixteen Event Order registers (one per Event) are added which indicates the order in which the events were completed externally.

 

 

C] Changes in ACM Registers:

Compared to ACM registers on BF50x, following are the changes made BF60x ACM registers:

 

1] Changes in ACM Control Register:

     -     CLKMOD bit is added to support the newly added Gated clock mode

     -     Couple of bits are added to use the Event Order registers

          -     Order Register Reset (ORST) bit has been added to clear all the Event Order registers in the software

  -     Automatic Order Reset Enable (AOREN) bit has been added to clear all the Event Order registers automatically in Hardware after detecting selected trigger.

          -     Trigger Select for Order register Reset (OTSEL) bit has been added to select the trigger for Auromatic Order register Reset.

 

2] changes in Timing Configuration Register (ACM_TC0):

The 8-bit Setup Cycle field of this register of BF50x has been expanded to 12-bit field in BF60x processor, resulting in specifying the set-up time cycles upto 4096 SCLKs compared to 256 SCLKs in previous ACM version.

 

3] Changes in ACM Status register (ACM_STAT):

In BF50x, single bit (ECOMP) in this register is shared by both ACM Timers for indicating event completion for the current trigger.

In BF60x ACM_STAT register, seperate event completion bits are provided for both the ACM Timers (ECOM1 and ECOM2)

 

4] Changes in ACM Event Status Register (ACM_ES):

Two extra bits are added to indicate whether all the enabled events of a perticular ACM Timer are completed for the current trigger or not.

These bits are named as ECOM0S and ECOM1S; and are essentially reflects ECOMP0 and ECOMP1 status bits in ACM_STAT register.

 

5] Changes in ACM Event Interrupt Mask Register (ACM_IMSK):

Two bits have been added, IECOM0 & IECOM1, to enable the Event Completion interrupt based on ECOM0S and ECOM1S bits in ACM_ES register.

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