Compared to the earlier Blackfin Processors, many new features have been added to the GP Timers module of BF60x.
1. Apart from the 3 operating modes in the earlier BF processors viz. PWM_OUT, WIDTH_CAP and EXT_CLK modes, there are additional modes introduced in BF60x.
a. Pin Interrupt Capture mode- In this mode, any active edges on either TMR_IN pin or TMR_AUX_IN pin can cause edge interrupt if enabled. The event on these input pins can cause the data interrupt latch TMR_DATA_ILATx bit to get set and issue a system interrupt request.Along with interrupt timer also generates trigger pulse of one SCLK on timer trigger line if it is enabled by unmasking resetting TMR_TRG_MASKx bit in timer trigger mask register.
b. Windowed Watchdog mode -With this mode,timer can monitor pulse width (width watchdog mode) or pulse period (period watchdog mode) on timer input line. It also compares measured value against minimum required value (Delay Register) and maximum value (Period Register) and generates interrupt appropriately.
c. Broadcast Write Feature - Broadcast feature provides means to update TMRx_WIDTH, TMRx_DELAY and TMRx_PERIOD register within more than one timer. It means with single PAB broadcast write, software can update either delay or period or width register of timer ranging 0 to 15.
2. Addition of Delay Start Feature
- A new register TIMER_DELAY is added which is to be programmed with the number of SCLK cycles the TMRx pin should wait after the corresponding TIMER_TMR_CFG register is programmed before asserting the pulse output.Initially, TMR_OUT pin remains in de-asserted state and it toggles to asserted state when Count= TMRx_DELAY register. Assertion sense of the TMR_OUT pin can be controlled with the PULSE_HI bit in TMRx_CONFIG register.
3. Trigger slave Functionality
- Timer can act as a Trigger Slave, meaning that it can be either started or stopped with a trigger master pulse originating from the TRU, depending on its TIMER_TMR_CFG.SLAVETRIG setting. Timer moves into run state if an active edge is seen on the trigger line. If a timer is already in run state then input event will not have any impact on timer state. Similarly if timer slave trigger mode bit is 0, timer comes to halt state if it is in running while input trigger pulse is seen. If timer is in already halt state then there is no impact on timer state in such case.
4. Timer Data and Status Interrupt Latch Registers
- Each Timer can generate a unique processor data Interrupt Request signal, if data interrupt is unmasked in the timer data interrupt mask register . A 16 bit W1C TMR_DATA_ILAT register records the generated interrupts so that the user can determine the interrupt source without reference to the unique interrupt signal.
Similarly, the TMR_STATUS_ILAT register indicate either occurrence of overflow or prohibited programming in a particular timer register provided the corresponding Timer is unmasked in the TMR_STATUS_IMASK register.It should be noted that the status is not reflected if it is masked in the TMR_STATUS_IMASK register.