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Have there been any modifications/additions in the Serial Port (SPORT) registers on BF60x processors?

Question asked by Prashant Employee on Mar 26, 2012

The architecture of Serial Ports on BF60x is different than that of previous Blackfin processors. There have been many enhancements as well. Refer

Accordingly major changes have been made in the SPORT registers of BF60x processor to support those modifications.

Below are important points to note about Serial Port registers on BF60x processor (for complete details refer Hardware Reference Manual):

 

1] SPORT Control register (CTL_x):

The control bits of SPORT_TCR1 (or SPORT_RCR1) and SPORT_TCR2 (or SPORT_RCR2) registers of previous BF SPORT are combined in a single 32-bit register known as SPORT control register (CTL_x).

Like the name suggests, it controls most of the Serial Port settings such as operating mode, serial word length, clock modes, frame sync type etc.

In addition, the SPORT status (SPORT_STAT) register has been removed from BF60x Serial Port register list. The Data Buffer status and error bits are included in this control register (not all bits of that register).

So, you may find this register resembles to Control register of SHARC Serial Port.

 

1.Control_Reg.jpg

 

A] Channel Enable Bits:

In Previous BF SPORT, the TSPEN (or RSPEN) bit of TCR1 (or RCR1) register enables the module. It also by default enables primary Data channel. The TXSE (or RXSE) bit in TCR2 (or RCR2) register enables the Secondary Data channel and takes effect only when TSPEN bit is set. So, primary Data channel can’t be disabled OR only secondary channel can’t be enabled.

But BF60x serial Port provides separate enable bits for data channels (so there is no redundant module enable bit). Primary Data channel can be controlled by SPENPRI bit; while secondary Data channel can be independent controlled by SPENSEC control bit. Setting one of these bits enables the module to start the serial port operation.

 

B] Following control bits are same as previous BF SPORT control register bits:

Bit Name

Same as this bit in BF SPORT control register

Function

 

DTYPE

TDTYPE field in TCR1, OR

RDTYPE field in RCR1

Controls the data format and companding enable

LSBF

TLSBIT bit in TCR1, OR

RLSBIT bit in RCR1

Controls data in LSB bit first or MSB bit first format

SLEN

SLEN field in TCR2

Selects serial word length

ICLK

ITCLK bit in TCR1, OR

IRCLK bit in RCR1

Controls whether serial clock is internally generated or externally supplied.

IFS

ITCLK bit in TCR1, OR

IRCLK bit in RCR1

Controls whether frame sync signal is internally generated or externally supplied.

FSR

TFSR bit in TCR1, OR

RFSR bit in RCR1

Selects framed mode or unframed mode of operation.

DIFS

DITFS bit in TCR1

Selects Data-dependent or data-independent frame sync.

LFS

LTFS bit in TCR1, OR

LRFS bit in RCR1

Selects active high or active low frame sync polarity.

LAFS

LATFS bit in TCR1, OR

LARFS bit in RCR1

Selects early frame sync mode or Late frame sync mode.

 

OPMODE

TSFSE bit in TCR2, OR

RSFSE bit in RCR2

Generates frame sync as normal pulse shape or in LR shape.

Used as operating mode select bit.

CKRE

TCKFE bit in TCR1, OR

RCKFE bit in RCR1

Drive output signals on one edge of the SPORT_CLK; while sample input signals on other edge of the SPORT_CLK

 

C] Following bits are added to use the enhancements made in the module.

Bit Name

Purpose

RJUST

This bit is used to enable the Right-justified operating mode of serial port

FSED

Selects sensitivity of frame sync as level-sensitive or edge-sensitive

TFIN

Provides Transmit Finish Interrupt (when configured in Transmit DMA mode)

GCLKEN

Enables Gated clock mode

SPTRAN

Configures serial port in Transmit mode or receive mode

 

D] The following bits has been used as status bits (These bits are read-only)

Bit Name

Purpose

DXSPRI

Primary Data Buffer status

DERRPRI

Primary Data channel Error

DXSSEC

Secondary Data Buffer status

DERRSEC

Secondary Data channel Error

 

-          The Data Buffer status bits are similar to TXHRE and TXF bits if configured as transmitter OR similar to RXNE when configured as receiver. It provides more details about this Data buffer status by indicating whether it is Empty, Partially Full or Full.

 

-          The Data Channel Error bits (DERRPRI and DERRSEC) are similar to TUVF (Transmit under-run) when SPORT is configured Transmitter; OR similar to ROVF (Receive overflow) when SPORT is configured as receiver.

-          There is no support for RUVF (receive underflow) or TOVF (Transmit overflow) error bits as it is there in previous BF SPORT. But those bits are irrelevant in BF60x SPORT, as it is either configured as Transmitter or receiver.

 

 

 

2] SPORT Control 2 register (CTL2_x):

Only two bits of this register are valid, which enables the SPMUX logic (enables internal routing of SPORT signals between two halves of SPORT).

2.Control2_Reg.jpg

-          CKMUXSEL: enables or disables serial clock multiplexing

-          FSMUXSEL: enables or disables Frame sync multiplexing

 

 

 

3] Divisor Register (DIV_x):

The 16-bit TCLKDIV (or RCLKDIV) and TFSDIV (RFSDIV) registers of previous BF SPORT are combined in a 32-bit single register, known as Divisor register (DIV_x).

3.DIV_Reg.jpg

-          CLKDIV = (SCLK1 / SPORT_CLK ) – 1

-          FSDIV = (number of serial clocks between frame syncs) – 1

 

 

 

4] Error Register:

This register holds the error status bits and it’s interrupt mask bits to trigger SPORT Status Interrupt.

4.ERROR_Reg.jpg

Bit Name

Purpose

DERRPSTAT

Primary Data channel error detected. Same as DERRPRI status bit in CTL_x register, but W1C

DERRSSTAT

Secondary Data channel Error detected. Same as DERRSEC status bit in CTL_x register, but W1C

FSERRSTAT

Premature Frame sync detected (FS error)

DERRPMSK

When set, triggers SPORT status interrupt

DERRSMSK

When set, triggers SPORT status interrupt

FSERRMSK

When set, triggers SPORT status interrupt

 

 

 

5] Multi-channel Control register (MCTL_x):

The Control bits in SPORT_MCMC1 and SPORT_MCMC2 multichannel configuration registers of previous Blackfin SPORT have been combined into a single 32-bit register, known as ‘Multichannel Control register’ (MCTL_x).

5.MC_Reg.jpg

A] Following control bits are same as previous BF SPORT Multichannel control register bits:

Bit Name

Same as this bit in BF SPORT MC register

Function

MCE

MCMEN bit in MCMC2

When set, enables multichannel and packed mode

MCPDE

MCDTXPE and MCDTXPE bit in MCMC2

When set, enables Multichannel DMA Packing

MFD

MFD field in MCMC2

Determines multichannel frame delay

WSIZE

WSIZE field in MCMC1

Determines window size. (different compared to WSIZE field calculation in BF SPORT)

WODFFSET

WOFF field in MCMC1

Determines window offset

 

B] The Following bits of SPORT_MCMC2 register has been removed from BF60x serial port:

-          MCCRM : 2X Clock Recovery Mode

-          FSDR : Frame sync to Data Relationship (H.100 mode)

 

 

 

6] Multichannel Select Registers (CSn_x):

In previous BF SPORT, the SPORT_MTCSn (Multichannel Transmit Select) and SPORT_MRCSn (Multichannel Receive Select) registers are used to select channels for Tx and Rx side.

In BF60x, since a serial port can be either configured as transmitter or receiver, the two groups of registers are replaced with a single group known as SPORT_CSn (where n=0,1,2,3). Usage of register is same.

 

 

 

7] Multi-channel Status Register(MSTAT_x):

The SPORT_CHNL register in the previous BF SPORT has been renamed as MSTAT_x, known as multichannel status register. It indicates the current multi-channel being serviced.

 

 

 

8] Data Buffer Registers (TXPRI, TXSEC and RXPRI, RXSEC):

Although BF60x SPORT can be configured as either transmitter or receiver, it incorporates separate Transmit Data buffer and Receive Data buffer for each Primary and Secondary Data channels. But only one type of buffers (TX or RX) are active as per enabled data channels. Programmer must not attempt to access the inactive buffers.

 

 

 

 

Additional Notes:

-          All registers are 32-bit wide.

-          Each SPORT half have it’s own registers (i.e. there is not a single register which is shared between the SPORT halves).

-          The naming of registers is SPORTnumber_Registername_SPORThalve.

               e.g. Serial Port control register of SPORT1_B serial port is denoted as SPORT1_CTL_B;

-      when using Crosscore IDDE, the header files of processor attaches REG before the register name. So, this register can be find as REG_SPORT1_CTL_B in the header file.

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