I can't see SD(480I) images ,Enclose is ad9889 configuration when input SD signal(480I).
I don't know why it doesn't work,please help me ,thanks.
Can you describe your system and how you are testing it. It could be any number of things including the monitor doesn't work with 480i over HDMI.
My system is a SDI to HDMI box,
it convert SDI signal to HDMI signal.
HDMI transmitter chip is ad9889b.
The HDMI signal is sent to a TV.
The TV can display 480i signal.
The quick start guide in the AD9889B Programming Guide found at http://ez.analog.com/docs/DOC-1741 has a list of required write. I noticed that the registers are not being set up per the quick start.
Also Video Format ID ox15[3:0] appears to set to 0x8 which is an undefined VID. Just follow the quick start and you should be OK. I can't give you direct instruction since you did not specify the input style from the SDI decoder.
The picture is my new configuration list.
My SDI decoder is a FPGA chip.
I have achieved HD and 3G(1080p50,1080p60) SDI signals from SDI to HDMI.
The EAV and SAV of 480i are 3FF 000 XYZ,it is different to ITU 656(3FF,000,000,XYZ)
Please help me to configurate ad9889b
From the configuration list I see that you've set it up for Input ID 2 which is 16 bit YCbCr (embedded syncs) This would be one 8 bit channel for the Ys and one 8 bit channel for CbCr.
From your EAV/SAV pattern of 3FF... and 4:2:2 Width (0x16[5:4]) you are expecting a 10 bit only input where YCbCr are interleaved on one 10 bit bus. Here's the miss-match. I'm not sure what input format you are trying to do, 10 bit YCbCr or 16 bit YCbCr.
Also when you specify AV Codes the code width must match the input bus width.
I sorry ,I give you some wrong information about video format.
The picture shows my signal format about 480I.
I think my first configuration list is right.
But I don't know why it doesn't work.
Please help me,thanks.
If I'm understanding the last picture correctly you are interleaving the embedded codes across 2 channels. Don't do this. Put 3FF, 000, 000, XYZ all on the Y channel. Some of our chips can handle interleaved embedded syncs like this but I don't see the bit's to control this in the AD9889B.
To verify the rest of the register settings I'll need to look at the schematic. You can use private email to send it to me.
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