The Serial PORT of BF60x is designed to include best features of serial ports on SHARC and Blackfin processors with some enhancements. Though it’s functional operations are same, some changes has been made to incorporate newly added features. Here are some of those important changes and enhancements compared to serial port of previous Blackfin processors (It is advised to refer Serial PORT chapter in the Hardware reference Manual for more details).
1] SPORT Architecture: The ADSP-BF60x processors feature three Serial Ports. The SPORT top module comprises of two half SPORTs (termed as A and B) with identical functionality. So, a serial PORT is sometimes also referred as full SPORT, while the two halves as HSPORTs.
Each half SPORT can be independently configured as either transmitter or receiver in any operating mode (i.e. with different control settings), so you may find these three SPORTs as six separate, independent serial ports. Similar to previous Blackfin serial ports, each Half SPORT has two data paths, primary(D0) and Secondary(D1) which allows unidirectional dual-stream transfers.
The two SPORT halves are denoted as SPORTx_A and SPORTx_B…where x represents Serial PORT number viz 0, 1 or 2. They have separate registers (so almost independent configuration) and five dedicated pins, named as signal name preceded by SPORT ID.
E.g. the SPORT0_A pins are denoted as SPORT0_ACLK, SPORT0_AFS, SPORT0_D0, SPORT0_D1 and SPORT0_TDV; whereas the pins of B halve of SPORT2 are SPORT2_BCLK, SPORT2_BFS….and so on.
There are major changes in SPORT registers and it’s bit fields. These changes can be find here.
2] Control signals sharing between SPORT halves: As an enhancement, the SPORT halves within a serial port can be optionally coupled together to share the some of the signals. A local multiplexing block, SPMUX, (integrated between SPORT and the PORT_Mux logic), provides the ability to route and share the clocks and/or frame sync control signals between the SPORT halves of the SPORT module. This is especially efficient when using a full SPORT for full-duplex data transfers (thereby reducing the total number of PORT pins required for the interface).
3] Operating Modes: The serial port of BF60x inherits all the operating modes as previous Blackfin processor supports. The protocol and control bits are similar. In addition, two modes are included to increase variety of protocols supported by serial ports. So, the operating modes it supports are:
- Standard DSP serial mode
- I2S mode
- Left-Justified mode
- Right-Justified Mode: aligns the data to the end of the frame sync (delays the start of word w.r.t. frame sync).
- Multichannel Mode: There are some changes w.r.t. multichannel mode in previous Blackfin. Refer.
- Packed mode: Same as multichannel mode, but frame sync shape is like LR clock. So, combination of stereo and multichannel mode. [This mode is available in SHARC serial ports].
4] Gated clock mode Support: In DSP serial, I2S and left-justified modes serial port can work in Gated clock mode, in which serial clock is active only when active data is being transmitted or received.
The serial ports of BF592 supports Gated clock mode only when it is configured in internal_clock-internal_FS mode. In addition, serial ports of BF60x support this mode in external_clock-external_FS mode as well.
5] Serial clock (& hence SPORT speed): The serial ports are capable of operating at SCLK1 speed (compared to SCLK/2 rate in previous Blackfin SPORTs)...but upto 83MHz max. So, when SPORT is configured to enable both data channels, the transfer speed can go be upto 2xSCLK1 (166Mbps) rate.
[Note: Serial Ports and it's associated DMA's operate in SCLK1 domain. SCLK1 is derived from SYSCLK]
6] Improved clock Granularity when serial clock is generated internally:
In previous Blackfin processors, if SPORT is configured in internal clock mode, then serial clock is calculated as: SPORT_CLK = SCLK / (2 × (DIV+ 1). So, SCLK is always divided by even divider to generate SPORT clock.
But in BF60x, the internal serial clock is calculated as SPORT_CLK = SCLK1 / (DIV + 1), allowing odd dividers as well, increasing the serial clock granularity.
7] Enhancement with respect to Frame sync (FS) signal:
Status flagging and optional interrupt generation for prematurely received external frame syncs: In external FS mode, if extra valid frame sync is received when an active frame is in progress (which is called as premature frame sync and it is invalid), then error bit of a status register is flagged to indicate this framing error. Optionally interrupt can be triggered in this situation, if programmed.
Configuring sensitivity of external frame sync as level-sensitive or edge-sensitive: The frame sync signal of the SPORT module of earlier Blackfin processors is level-sensitive. Keeping this legacy feature, the serial ports of BF60x also provides an option to configure this signal as edge-sensitive signal. (This feature is available in some of the SHARC serial ports)
8] PACK Enable: For serial wordlength less than 16 bits, BF60x SPORTs can optionally enable 16-bit to 32-bit word packing (if receiver) or 32-bit to 16-bit word unpacking (if transmitter), thereby reducing the internal bus bandwidth.
9] SPORT DMA features: Similar to previous Blackfin processors, data transfers in serial port can be performed in core mode as well as DMA mode. BF60x processor provides one dedicated DMA channel per each SPORT half (which is common for both data lines).
Like all DMA channels of BF60x processors, the SPORT DMA also provides advanced features like signaling TRU about completion of work-unit (this signal can used by Trigger slaves to take the action on this event) or accepting trigger from TRU for the start of transfer. For complete details of these features refer Hardware reference Manual.
When using DMA in transmit mode, a Transfer Finish Interrupt (TFI) can be used to make sure that the last word of the transfer has been shifted out of the transmit shift register (i.e. external transfer has been completed). This feature can be helpful if SPORT disabling is required as soon as completion of transfer.
10] Minimum allowable serial word length: Similar to serial ports of previous BF processors, each SPORT half can independently handle word lengths upto 32 bits. But the minimum allowable word length has been changed to 4 or 5 depending on operating mode selected. Refer HRM for more details.
11] FIFO Size: The 16-bit x 8-deep FIFO in Blackfin serial ports has been changed to 2-deep or 3-deep FIFO in BF60x serial ports.
12] Interface with the ADC Control Module (ACM) block: Similar to BF50x processor, the control signals from ACM module can be internally routed to one of the halves of SPORT1.
The attached file can be used as reference to understand the important differences between serial ports on SHARC (perticularly ADSP-2146x), Blackfin (typically BF537) and BF60x.
I tried to add few simple codes to understand programmability of BF60x serial ports. Those can be find here.