Are the SHARC and TigerSHARC link ports compatible? How can I interface them?
The SHARC link port and TigerSHARC link port interfaces look similar, but their protocols are different and hence they are not compatible. For instance the SIMD SHARC link ports are sampled at only one edge of the clock, while the TigerSHARC link ports are sampled at both the edges of the clock providing higher throughput. Even the protocol is different between the two and hence they cannot be interfaced gluelessly.
One can always design a CPLD or a simple gluelogic to make the SHARC link port look like a TigerSHARC link port in order to interface them together.
I have a question on the LACK sample time for the Link port transmitter.
we can see in the SHARC21469 manual, it says "The transmitter samples LACKx driven by the receiver at the beginning of each word transmission (that is, after every 4 bytes)." so my question is
1) Will the transmitter sample the LACK at the falling edge or rising edge of the internal LCLK?
2) When transmitter detect LACK is deasserted, when will it sample the LACK again, in next internal LCLK cycle ?
3) When transmitter detect LACK is asserted from deasserted state , when will it drive LCLKx low out? should that align with its internal LCLK cycle or align with the moment that LACK is asserted?
The LACK is sampled at the the rising edge of internal LCLK.
The LACK is sampled again at the rising edge of LCLK following the fourth byte transmission of the previous word.
The LCLKx low out alligns with ithe internal LCLK after LACK is deasserted. It does not allign with the moment LACK is asserted.
Hope that helps.
Thanks for your reply.
So for link port transmitter, it will sample LACK at the rising edge of LCLK following the fourth byte transmission of the previous word. if the LACK at this moment is deasserted, it will continue to sample the LACK at each rising edge of next internal LCLK until it sample the LACK turn to asserted state, is my understanding right?
Yes, your understanding is correct.
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