What is the maximum speed of operation for SPI on SHARC Processors?
The maximum speed of operation for SPI peripheral on SHARC depends on whether the SPI operates in master or slave mode.
For 2136x, 2137x family
SPI master mode - max frequency is 1/8 of peripheral clock frequency.SPI slave mode - max frequency is 1/4 of peripheral clock frequency.
For 2126x family
SPI master mode - max frequency is 1/8 of core clock frequency.
SPI slave mode - max frequency is 1/4 of peripheral clock frequency.
With regards to 21375
CCLK is set to 262.144Mhz
Can i use SPI CLK at (PCLK=262.144/2 )/ 8 = 41.7Mhz
We are finding the SPI doest work when it SPIBAUD is set to lower than 100 .
Please let me know with regards to this .
>>Can i use SPI CLK at (PCLK=262.144/2 )/ 8 = 41.7Mhz
with the core clock of 262.144 the maximum SPI CLK you can get is 1/8* peripheral clock = 1/8*131.072 = 16.384MHz.
>>We are finding the SPI doest work when it SPIBAUD is set to lower than 100 .
Not clear what you are looking for here . What frequency are you looking to acheive.Please note that Bit 15 to 1 in the SPIBAUD register give the SPI Baud rate value. If you are looking to divide the SPICLK with a baud rate of 100, bit 15:1 should have a value of 0x64.
Hope this is what you are looking for.
I trying to configure SPI clock frequency on ADSP-21369 EZ-KIT LITE 2.1, but with no sucess.
It is written on ADSP-2137x SHARC Processor Hardware Reference that SPI clock frequency is given by SPICLK = PCLK/ (8 * BAUDR) (Page A-148). The problem is that SPI clock frequency doesn't have the expected frequency.
My core clock is 393.216 MHz, so my peripheral clock is 196.608 MHz. I'm setting BAUDR to 4 (0x04) so the expected SPICLK was 8.192 MHz, but...no SPICLK is aprox. 24 MHz (i watched it on oscilloscope). It seems that it is doing PCLK/(2*BAUDR) and not PCLK/ (8 * BAUDR).
My SPI setup code is,
*pSPICTL = (TXFLSH | RXFLSH) ; // Flush Transmit/Receive buffer
*pSPIFLG = 0; // Reset FLAG register
*pSPICTL = 0; // Reset Control Register
/* Setup the baud rate
*pSPIBAUD = 0x04;
*pSPIFLG = 0xFD02;
*pSPICTL = (SPIEN | SPIMS | WL8 | TIMOD1 | MSBF | CPHASE | CLKPL);
SRU(SPI_MOSI_O,DPI_PB08_I); //Connect MOSI to DPI PB1.
SRU(DPI_PB06_O, SPI_MISO_I); //Connect DPI PB2 to MISO.
SRU(SPI_CLK_O, DPI_PB10_I); //Connect SPI CLK to DPI PB3.
SRU(TIMER0_O, DPI_PB04_I); //CNV signal to activate ADC.
SRU(SPI_FLG1_O, DPI_PB12_I); //Chip select Serial2Parallel
Can you please give me a help on this?
What you see is expected. The confusion seems to be because of two things:
1) It seems to be a mistake in the HRM. The expression should indeed be:
SPICLK = PCLK/ (4 * BAUDR)
Thanks for pointing this out. I shall take required actions to get this fixed in the next HRM update.
2) The BAUDR field is located from bit 1 to bit 15 of the SPIBAUD register, so SPIBAUD = 0x04 actually means BAUDR = 2.
Because of these two reasons, the expected SPICLK for SPIBAUD=4 should be = 196.608/(4*2) = 24.576 MHz which is what you see.
If you want SPICLK=8.192 MHz, you will need to use BAUDR = 6 and SPIBAUD register should be initialized to 0xC.
Hope this helps.
Thanks for your answer, it's working correctly now!
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