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Has there been any modification in any of the existing RSI features on BF60x processors?

Question asked by Mitesh Employee on Mar 22, 2012

Yes, the following two features have been modified/enhanced in BF60x processors:


  • Option to disable CRC check - Memory cards don’t send CRC for few selected commands. Existing RSI takes the stuffed bits coming from the card as CRC and gives a CRC check failure interrupt. To overcome this, a bit is added in the RSI command register where software can program whether CRC check can be optionally disabled for such commands.


  • DataEnd Interrupt generation– In existing RSI, DataEnd Interrupt is raised when the data counter reaches 0. This has been modified in the new version of RSI on BF60x processors. DataEnd interrupt is delayed in data write operation if the card indicates a busy condition by pulling the DAT0 line low. This interrupt will be raised once the DAT0 line is released to high.