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AD9889B Clk related noise

Question asked by alanf on Mar 18, 2012
Latest reply on Mar 19, 2012 by GuenterL

Hi, we are in the final stages of developing an IP decoder to 720P HDMI output device.  We seem to have a specific noise issue with the 74meg25 clock. when examining the noise spectra for emc compliance we have a comb effect extending on 'ALL' harmonics to 742meg and a little beyond.


The chip is being driven by an off pcb DSP, the clock is generated via IDT308 chip. we have narrowed the field of possible noise sources via a range of experiments.

1. Driven the whole design from 75meg oscillator to erradicate 308 clk chip pll circuitry, The display still works, we know it is not within spec when running from 75meg. 

2. We have run the DSP sync clock from 74meg25 and the AD9889B from 90meg, not within spec, got a stripy display, but from our point of view the noise followed the 90meg AD9889 side of the design, this allowed us to discount the DSP and memory accesses.

3. Powered the whole design from local 75meg oscillator dead bugged next to AD9889B and back feed the DSP clock line, an attempt to discount the Clk line tracking between the AD9889B and the normal clock source.  All 1v8 pins are isolated with ferrite and 10u + 100n plus occasional 560pf. 

4. Noise problem still present when AD9889B clocked with no data on the vid input pins, get a green display. Not a real world test but allowed us to discount the vid_data lines from the dsp as a source.

5. 4layer pcb for AD9889B. tried local 1v8 LDO.

6. registers 0xa2 and 0xa3 set to 0x87 normal drive levels, tried lower values no difference. tried 100R in clock line, reduced noise by approx 3dB.


As you can read, getting quite desperate.  Any shared experiences would be most welcome.  No problem with the display itself, only the noise generation.  I must have done something wicked along the way.




PS find attached schematic to HDMI section