What state do the digital outputs on the ADV7180 go to during a reset ?
During reset the INTRQ pin of the ADV718 goes open drain. An external pull-up resistor is needed to make this pin go high during reset.
All other digital outputs (including the P7:P0 video pixel output port pins, LLC, Hsync, Vsync, Field, SFL) go into an underterminded state during a reset.
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