I'm trying to attach an FPGA to the ADSP-21479's AMI. Looking at the hardware reference manual for the ADSP-214xx, in section 3 for the AMI, it says that the data for a read is sampled on the rising edge of the SDCLK at the beginning of the hold period (when the /AMI_RD line goes high). The FPGA obviously doesn't have access to SDCLK, though, so how does it know when to tri-state the bus? On the DSP's side, I can use the Idle Cycle (IC) bits in the AMICTL register to give the FPGA plenty of time to release the bus, but simply putting in a few clock cycle delays on the FPGA doesn't seem reliable. Is there a better way?
On a related note, when the reference manual says "cycles," is that the time it takes to do one byte of data transfer, or one SDCLK period?