I’m designing a system where we want to use an ADV7604 as a video input driving the pixel bus into a TI SoC device. The output timings of the video bus from the ADV7604 as given in the datasheet as t11 and t12 on page 6 are only specified for typical values.
I’ve read the thread about the output timings on the ADV7612 - http://ez.analog.com/message/43673#43673, and I interpret the answer to be as follows:
Sweep the DLL tap setting over all the possible values and find the range over which it gives valid video data (for a known input picture). Pick the middle of this range and assume that all boards will be fine.
Whilst this method is sensible, I’m not happy about it because it relies on the variation of t11/t12 to be small over process, voltage and temperature. As this variation was not given in the previous thread, I have to assume that it’s not known.
For any given board on the bench/assembly line, assuming that we have a range of tap settings over which the input is valid – e.g. taps 16 through 25 on GuenterL’s board then we can be happy that that specific board is working right there with some margin to spare. However, if we were to heat up that board (remaining within the allowed operating range for all devices) and repeat the test, then I would expect that the window of valid DLL taps would move, grow or shrink. Variations between boards are of more concern - the ADV7604 will surely have some inherent variation in its output timings between devices which are on the fast and slow end of the process and the voltages on the board will vary slightly due to the finite tolerance of the power supply set resistors and the reference voltages within the regulators.
If these changes are very small then that’s great and it should all work without issue. However the problem is that without knowing how this window changes over these parameters, I can’t be sure that choosing the middle of the range (20 or 21) will still give working video at one extreme. If the window shifts in one direction by five taps then this will no longer give a valid output.
I see two solutions here:
- ADI could measure/determine the spec for the part at the worst-case DLL setting and over process, voltage and temperature to give maximum values for t11 and t12.
- We could find the value experimentally over all process, voltage and temperature. As part of our standard design verification, we test the functionality at the top and bottom of the voltage range and the top and bottom of the operating temperature range. This covers two of the three parameters, but we can’t usually test for the extremes of process, so we have to hope that we have enough spare margin to accommodate it. If you could send us examples of the fastest and slowest silicon for this part then we could experimentally verify that the part works at all extremes of operation.