SRAM and SDRAM compared, how many SCLK cycles are needed for one 16-bit memory transfer when executing directly from that memory with Cache OFF?
For external memory execution with cache OFF, a group of four 16-bit words are read sequentially from external memory. This is followed by latency cycles and again a group of four 16-bit words. In case of SDRAM, for these 4 words, each word takes 1 SCLK cycle. In case of SRAM, each word takes 2 SCLK cycles. The latency cycles between the groups of four words depend on several parameters, and this would decide which of the two memories is faster.
Parameters that affect the latency:SRAM:
a) SCLK frequencyb) CCLK/ SCLK ratio which decides the number of idle cycles after each read. In general: higher the ratio, lesser are the number of idle cycles. c) Configuration of the AMC (Asynchronous Memory Controller)
SDRAM: a) SCLK frequency (which equals SDCLK frequency)b) Configuration of the SDC (SDRAM Controller).
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