I use AD9959 evaluation board to design signal. when I load the ad9959 software, an error occurs,"the evaluation board doesn't seem to have a ref_clk".
here , I use the 25MHz cystral as the ref_clk of AD9959. W11 is connected to cystral. the AVDD power is separated from DVDD.
In this mode ,I find the cystral can't generate oscillating signal in the oscillograph. I want to ask whether the C21 ,C22 should be remove from the board. these two caps will have impacted on cystral signal.