I have a customer who is considering connecting the EN pin to VDD to keep the switch permanently enabled, but wanted to know if there is a chance that any digital noise on the IN pin could couple to VDD via the EN pin. Is it recommended to connect EN this way or should it be tied high from a logic rail (3.3V or 5V)? See below.
I am using the ADG1419 SPDT switch in my analog processing to switch in a gain resistor in one place and switch the signal routing in another. The switch has VDD/VSS of +/-9V analog, but is controlled by digital logic to make the switch and by a digital enable pin.
I have looked and can't find any issues with tying the enable pin high with the analog 9V supply, but I am concerned about digital noise getting into my circuit through the EN pin and the analog supply. This is a "set it and forget it" setting and will not be cycling during data acquisition, but I don't inadvertently want to give digital noise a path through the swtich enable.
Alternately I can enable it with 9V digital, but that would require bringing the digital supply into the analog portion of the circuit.