Is the AD9789 able to work using CMOS interface for data signals and LVDS for the sync signals (DCO and FS)?
The configuration is possible, but the DPG2 does not support such a configuration, so the eval board cannot be configured this way when used with the DPG2. There is limited data for such a configuration. All data in the data sheet was taken with both control and data either in CMOS or in LVDS mode.
I understand that the datasheet is focused in CMOS or LVDS. But, was the mixed mode (data CMOS, clks LVDS) operation tested?
The functionality has been tested and confirmed working, but there is no performance data taken with the mixed configuration.
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