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How to do both clock buffering and voltage shifting in a buffer?

Question asked by CodeWarrior on Mar 5, 2012
Latest reply on Mar 5, 2012 by pkern

Hi everyone,

 

I was wondering if a clock distribution guru could help me out...There's a 3.3V LVCMOS clock output coming out of my A/D, and I'd like to move that into an FPGA using the clock-capable pins on the FPGA that exist for that very purpose. Unfortunately, I ran out of 3.3V clock-capable inputs on the FPGA, and I’m wondering if you know a way to both buffer and voltage shift a clock signal that then goes into a 1.8V clock-capable FPGA pin. I have a 3.3V 25MHz LVCMOS clock and I’d really like to do two things:

 

  • Buffer the clock signal with a low-propagation-delay and low jitter clock buffer.
  • Convert the voltage from 3.3V LVCMOS to 1.8V LVCMOS.

 

I can think of a way to do the reverse – series terminate to get 50 ohms, AC-couple the 1.8V signal, diff terminate it with high-value resistors to 3.3V, and then put it into a 3.3V CCIO pin. That’s easy… Don’t know how to do the reverse though. Is there an AD device that can do this with some external components?

 

Thanks in advance for any help...

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