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AD9747 - input clock swing

Question asked by k.suchecki on Mar 3, 2012
Latest reply on Mar 6, 2012 by larrywelchusa

Hi,

In my design I would like to use AD9747 DAC however I have few questions about CLOCK input.

 

In my design, there are two possible clock sources - first is LVDS from FPGA and second will be used in case of external synchronization. Therefore I plan to use clock multiplexer/buffer ( CDCLVD1204 (LVDS) or CDCLVP1204 (LVPECL) or maybe you can recommend something from analog).

 

The typical value of "Differential Peak-to-Peak Voltage" for CLKP/N is 800 mV, so it is closer to LVPECL than LVDS, but the maximum output swing from CDLVP1204 is 1350 mV and if I put it on top of 400 mV input common mode voltage I get close to absolute maximum rating (-0.3V).

 

The datasheet says that CLKP/N input levels are not directly LVDS compatibile but still the LVDS clock can be used. However, the minimal "Differential Peak-to-Peak Voltage" is 400 mV and LVDS swing is typically 350 mV.

 

Q1: Can I use LVDS swing or LVPECL is preferable (single port mode)? If LVPECL, should I add clamp diode (as in Fig. 30 of the datasheet)?

 

Q2: Do you recommend using separate voltage regulators for CVDD18 and DVDD18 or can I use single 1.8V source (maybe with additional bypass capacitors)?

 

Thanks for your help.

 

Kind regards,

Karol Suchecki

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