AnsweredAssumed Answered

fine frequency tunning for high speed ADC clock

Question asked by FHC on Mar 2, 2012
Latest reply on Mar 6, 2012 by JLKeip

Hello Guys

My name is Fernando, I work for the Brazilian National Synchrotron Light Source.

 

We are designing a fast and broadband four channel digitizer for beam diagnostic pourposes for the next Brazilian light source. The ADC AD9467BCPZ-250 is a natural option for our design, since there is no other 16-bit faster ADC.

 

So we need to clock these four ADC´s with extremely low jitter signal to get the best SNR possible since the input signal is 500 MHz, so in this case we are using the under sampling technique. The frequency planning is:

 

We need to lock que clock signal for this 4 adc´s with a external frequency of 500MHz +-1 MHz divide by 800 (any frequency from 623.75 KHz to 626.25 KHz ).  For the ADC´s We need to generate the frequency of:  input lock signal*188, or 248 or 376... besides that we need to have the abilit to generate a fine frequency tunning like: input signal*188+- dozens of Hertz (e.g. 10 or  15 Hz). in a range of 1 Khz or more!

 

So whats the components from Analog Devices has this ability? how can i configuee these component?

Could give an idea whats the BW of the phase noise I have to considerer to calculate the jitter for these  ADC´s? I guess the most common specification is 12 Khz to 20 Mhz, but is not pratical for data aquisition, i thing the close in phase noise is important...

 

So guys, thanks in advance!

 

 

Fernando Henrique Cardoso

Beam Diagnostics Group (DIG)

Brazilian Synchrotron Light Laboratory (LNLS/CNPEM)

Campinas - Brazil - P.O.Box 6192 - ZIP Code 13083-970

Tel: +55 19 3512-3517 ou 3512-1144//// Cel phone: +55 19 82156023

Fax: +55 19 3512-1004

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