I am looking into a design that would use link ports from a 21469 (or 21161) to create a high speed interface to a Blackfin 527.
The idea is to use the PPI as a receiver and EBIU as a transmmitter. This would be much faster than a SPI or SPORT link.
The EBIU / Link Port Interface is not much different than the PDAP - EBIU inteface disccussed in EE-254.
My question concerns the PPI - Link Port interface where the PPI is configured as an 8 bit receiver.
It seems to me that a Blackfin GPIO could connect to PPI_FS1 and LACK. This would trigger both the SHARC to transmit and the PPI to receive.
The link port would send 32 bit data unpacked in four bytes. The first word would be a dummy word to account for the PPI delay (programmed accordingly to discard part of the first word). I think this means that the SHARC packet would be one 32 bit word longer than the
Here is my concern (from the 527 Manual):
"When the PPI_CLK is not free-running, there may be additional
latency cycles before data gets received or transmitted. In RX and
TX modes, there may be at least 2 cycles latency before valid data is
received or transmitted."
"Due to clock domain synchronization in RX modes with no frame
syncs, there may be a delay of at least 2 PPI_CLK cycles between
when the mode is enabled and when valid data is received. Therefore,
detection of the start of valid data should be managed by
This doesn't sound very deterministic. I don't understand the fine
details of the PPI. A timing diagram in the manual would be helpful.
The Link port clock is discontinous which may complicate the issue.
Any ideas or suggestions?