I'm not able to change the clocks on BF561. Can you help?
Follow the steps mentioned below to change the clock on BF561 processor.
1. Enable the wakeup interrupt from PLL for both cores SICA_IWR0 from Core A and SICB_IWR0 from Core B2. Write desired value to PLL_CTL (or VR_CTL if Voltage regulator) from Core A3. Put both cores into Idle (use a semaphore if necessary)4. Wakeup interrupts for both cores will be generated when the PLL (or VR) is ready
5. PLL_DIV can be written anytime without Idling both cores. As long as the MSEL and DF control bits in the PLL Control register (PLL_CTL) remain constant, the PLL is locked.
Refer to Look at Video In Out example in VDSP installation which configures the PLL.
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