In the Hardware User Guide (UG214), in section 8.16, it lists three "Important" criteria needed for the TMDS clock detection function read at Addr 40, register 0x6a, bit 1, to work. I have found that there is one more setting that is needed. HDMI Register 0x9D must be set to 0x02 for this function to work. This register is not documented so I have no idea what it does.
Please add this to the document in the next update.