AnsweredAssumed Answered

AD9910 disable DRG while DRCTL high leads to unexpected behaviour

Question asked by JHK on Feb 24, 2012
Latest reply on Mar 20, 2012 by DSB

Hi all,

 

I've stumbled across the following problem which I don't understand.

 

If the DR ENABLE bit (CFR2:19) is unset while DRCTL is high, and the DR is subsequently re-enabled (with DR still high), the DR accumulator can't be cleared, neither by autoclear (CFR1:13 set plus I/O update) nor by normal clear (CFR1:12  set plus  I/O update, followed by CFR1:12 unset plus I/O Update). In both cases, enabling the DR results in an immediate jump to the higher limit.

 

All of this works as expected if the DR is previously disabled with DRCTL low. 

 

I can work around this, obviously, but I'd like to know if this is a bug or a misunderstanding on my part.

 

Thanks!

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