I have a BF561 connected to an FPGA through PPI0 in 16-bit mode. PPI0 is configured in transmit mode with the FPGA supplying a continuous PPI clock. I have figured out how to generate FS1 (frame sync 1) that is active during the time that the data is being output by PPI0 (with one cycle of delay at the beginning of the transfer). The data that gets transmitted consists of seven smaller blocks of data, all equal in size. All seven blocks are transferred as a single DMA-PPI transaction.
What I need to be able to do is to have FS2 (or FS3) go active during the transfer of one of those seven smaller blocks; just as FS1 is active during the transfer of all seven blocks, FS2 is active for just one of the blocks. I'm specifying FS2 because this signal needs to be synchronized to the PPI clock (which leaves out using a flag bit) and it cannot be one of the PPI data bits. I'm working at the Blackfin register level and cannot find a register that allows me to delay the assertion of FS2. The PWM mode of the timer would work if I can delay when it starts. The transmitting of this data is not repetitious in a way that would allow me to use the periodic mode of the PWM timer. These frame syncs are internally generated.
Is there a way to delay the assertion of FS2? I can't find a register in the timer that will do this.
I did find an ADI_PPI device command code that indicates that this capability should be there. In the ADI_PPI_CMD_SET_TIMER_FRAME_SYNC_x, the ADI_PPI_FS_TMR pointer that is passed in has an argument (enable_delay) that is "the number of PPI CLKs that a sync signal must be delayed before it can be enabled." This sounds like just what I need. If this is the case, how is this programmed using just the registers and not the ADI_PPI device?
I'd appreciate any help you can give.