I have a problem when processing 1080p video on our new videoboard.
We are using three ADV7611 receiver devices as DVI input sources and one AD9889B transmitter device as the output source and between
a FPGA. One of the input sources has a PC connected. I have set up this device to DVI RGB 4:4:4 60Hz computer graphics and have done the same configuration of the AD8998B transmitter. When receiving all the videomodes in the DVI specification, (ranging from VGA to UXGA) I have a nice good PC desctop picture running on my 23" DVI monitor (1080p as prefered native), but when I try to set my computer graphics to generate a 1080p resolution or above I get a pc desctop picture with poor contrast. If I open a small prompt window and dragging it to the far left side on the desctop, (meaning trying to move it out of sight on the left side if the screen), I get blurring shadows in my pc desctop picture.
The DVI specification allows a pixel clock up to 165 Mhz in single mode. This is equal to the Vesa UXGA mode (161 MHz pixel clock).
If you read the DVI specification it allows you to process videomodes above UXGA mode but only if you use reduced blanking.
When measuring with my 1 GHz oscilloscope I can see that the PC praphic is sending approx. 138.5 MHz pixel clock when sending 1920x1080p mode (= reduced blanking). When connecting the computer directly to my 23" DVI monitor the picture is nice and good so the "problem" must be on the videoboard, ;-). I have put the PC device receiver output signals, (24-bit Pixel-bus, Vs, Hs, DE and Pixel-clock), directly through my FPGA, (meaning not using any input or output registers or other processing or locking to PLL:s and stuff like that in the FPGA), just mapping it from the input pins to the output pins of the FPGA. The problem remains. Do you somehow have to tell the ADV7611 receiver device or/and the AD9889B transmitter device when the case is that they must handle reduced blanking? If yes, how would I do that? I'm aware of the difference between the Vesa standards(computer graphics VGA-UXGA) and the CEA standards(xxxp&i, 720p, 1080p etc.)
Vesa use front and back porch together with H- and V-syncs to define the blanking area while the CEA standards have transformed this back & front porch to a DE, Data Enable signal (active high= active pixels/lines, active low= blanking in form of front & back porch + H- and V-syncs). In many of today modern displays there is no need for H- and V-syncs. (The display sence active pixels/lines , the rest is blanking).
Is there anyone of you that have faced this cind of problem?