The ssync; instruction does not seem to work on the Blackfin processors. I have done the following test to prove the issue:
• Write to a location on Asynchronous memory bank 3
• some assembly code
• Read from Asynchronous memory bank 1
This test is done in 2 cases
• X cycles of Write Access time for Async Bank 3
• Y cycles of Write Access time for Async Bank 3 (X > Y)
I probed on AMS3/ and AMS1/ signals, while triggering the scope on the rising edge of AMS3/.
I could see that the time interval between the rising edge of AMS3/ and the falling edge of AMS1/ is not the same in the two cases. The interval is smaller for X WAT case (X>Y). Some instructions seem to get executed while the AMI operation is taking place. Is ssync not doing it's job?