AnsweredAssumed Answered

BF-547 U-boot fail

Question asked by HansXie on Feb 21, 2012
Latest reply on Feb 21, 2012 by Aaronwu

Hi,

 

I happen to U-boot BF547 failed as follow:

1. BF547-6A, running 600M

2. 25M Osc

3. there is only 100M/120M fsclk selection for DDR,

4. DDR with133M support

 

question is: 100M U-boot ok, but 120M U-boot failed, following is print out: what is happened?

 

-----------------------------------------------------------------------------------

 

 

CTRL-A Z for help |115200 8N1 | NOR | Minicom 2.1    | VT102 |      Offline                                              

 

 

[root@localhost ~]# bfin-linux-uclibc-ldr /root/u-boot.ldr /dev/ttyS0 && minicom

 

 

Loading LDR /root/u-boot.ldr ... OK!

 

 

Opening /dev/ttyS0 ... OK!

 

 

Configuring terminal I/O ... OK!

 

 

Trying to send autobaud ... OK!

 

 

Trying to read autobaud ... OK!

 

 

Checking autobaud ... OK!

 

 

Autobaud result: 115200bps 49.766mhz (header:0xBF DLL:0x1B DLH:0x00 fin:0x00)

 

 

Sending blocks of DXE 1 ... [2/12] (17%)[board said: ABacC#abcdgjDa<b]

 

 

[board said: chij?!k��<�C�Ƒ�2����"��:���!��]

 

 

[board said: �%�jR

 

 

OK!          

 

 

You may want to run minicom or kermit now

 

 

Quick tip: run 'ldr <ldr> <tty> && minicom'

---------------------------------------------------------------------------------

 

 

 

 

 

 

 

following is my  U-boot configure:

 

 

 

u-boot配置如下:

 

 

//#define BFIN_BOOT_MODE       BFIN_BOOT_UART

 

 

 

 

 

     
/* CONFIG_CLKIN_HZ is any value in Hz                            */

 

 

        
#define CONFIG_CLKIN_HZ          25000000

 

 

    
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */

 

 

      /*                                                  1=CLKIN/2    */

 

 

        
#define CONFIG_CLKIN_HALF               0

 

 

    
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */

 

 

    
/*                                               1=bypass PLL    */

 

 

       
#define CONFIG_PLL_BYPASS               0

 

 

   
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */

 

 

    
/* Values can range from 1-64                                    */

 

 

       
#define CONFIG_VCO_MULT      24  //cpu
的主频

 

 

      /* CONFIG_CCLK_DIV controls what the core clock divider is       */

 

 

  
/* Values can be 1, 2, 4, or 8 ONLY                              */

 

 

      
#define CONFIG_CCLK_DIV    1

 

 

     /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */

 

 

  
/* Values can range from 1-15                                    */

 

 

    
#define CONFIG_SCLK_DIV    5  //cpu
的外频

 

 

 
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider     */

 

 

 
/* Values can range from 2-65535                                 */

 

 

  
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                  */

 

 

   
#define CONFIG_SPI_BAUD 2

 

 

  
#if (BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)

 

 

   
#define CONFIG_SPI_BAUD_INITBLOCK 4

 

 

   #endif

 

 

 

 

 

#define CONFIG_MEM_SIZE             128/256            /* 128, 64, 32, 16 */

 

 

#define CONFIG_MEM_ADD_WDTH     11            /* 8, 9, 10, 11    */

 

 

 

 

 

#define CONFIG_EBIU_DDRCTL0_VAL              0x218A8400//0x218A83FE(131M,one bank),0x218E848C(150M,two bank CL=3)

 

 

#define CONFIG_EBIU_DDRCTL1_VAL              0x20012222//0x20022222(131M,one bank),0x20016323(150M,two bank)

 

 

#define CONFIG_EBIU_DDRCTL2_VAL              0x00000031 //0x00000021(CL=2),0x00000031(CL=3),0x00000061(CL=2.5)

 

 

 

Outcomes