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AD9912 SYSCLK PLL resdual phase noise

Question asked by stevesch on Feb 17, 2012
Latest reply on Feb 21, 2012 by stevesch

Does anyone have any residual phase noise data for the AD9912 SYSCLK PLL clock synthesizer?  I'd like to use a low-noise 100 MHz OCXO source for the clock and multiply it up to 800 MHz to clock the DDS core.  I can multiply the 100 MHz to 800 MHz practically noiselessly externally but with lots of components.  I'd much rather use the AD9912's clock doubler and PLL but I need to know how noisy it is.  Thanks a lot!  Steve