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AD9211 in ddr mode

Question asked by Shuric on Feb 17, 2012
Latest reply on Sep 11, 2017 by David.Buchanan

I use AD9211-200 adc in ddr mode with Cyclone III FPGA, and have problem with digital data interface. The image shows data that i get from adc for sample rate 200 MHz and input sine wave 200.05 MHz.

data.JPG

Bit 0 from adc allways zero. Bits 4 and 5 are not consistent.

In what may be the problem?

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