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BF547 can not start when it uses CCLK 600MHZ and SCLK 120MHZ .

Question asked by Yeahfeng on Feb 16, 2012
Latest reply on Feb 24, 2012 by PrasanthR

BF547 can not start when it uses CCLK 600MHZ and SCLK 120MHZ ? But it can start up when uses CCLK 525MHZ/600MHZ and SCLK 131MHZ/150MHZ .

my configure:

/* CONFIG_CLKIN_HZ is any value in Hz                            */

#define CONFIG_CLKIN_HZ             25000000

/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */

/*                                                  1=CLKIN/2    */

#define CONFIG_CLKIN_HALF                  0

/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */

/*                                               1=bypass PLL    */

#define CONFIG_PLL_BYPASS                   0

/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */

/* Values can range from 1-64                                    */

#define  CONFIG_VCO_MULT                     24  //cpu的主频

/* CONFIG_CCLK_DIV controls what the core clock divider is       */

/* Values can be 1, 2, 4, or 8 ONLY                              */

#define CONFIG_CCLK_DIV                   1

/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */

/* Values can range from 1-15                                    */

#define CONFIG_SCLK_DIV                    5  //cpu的外频

/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider     */

/* Values can range from 2-65535                                 */

/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                  */

#define CONFIG_SPI_BAUD               2

#if (BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)

#define CONFIG_SPI_BAUD_INITBLOCK     4

#endif

 

#define CONFIG_EBIU_DDRCTL0_VAL              0x218A8400    //0x218A83FE(131M,one bank),0x218E848C(150M,two bank CL=3)

#define CONFIG_EBIU_DDRCTL1_VAL              0x20012222   //0x20022222(131M,one bank),0x20016323(150M,two bank)

#define CONFIG_EBIU_DDRCTL2_VAL              0x00000031   //0x00000021(CL=2),0x00000031(CL=3),0x00000061(CL=2.5)

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